1. Field of the Invention
The present invention generally relates to a motor driving device, a method of adjusting the same, and an information storage device, and more particularly, to a motor driving device which performs current-feedback PWM drive, a method of adjusting the same, and an information storage device.
2. Description of the Related Art
In an optical disk, an actuator is often used for focusing, tracking and moving a recording head in the radial direction of a recording medium.
Current control is conducted for the servo control of the actuator. PWM (Pulse Width Modulation) control which requires low power consumption is also conducted, taking advantage of its inductance characteristics. In the PWM drive, a current flowing in the actuator is detected, and the current control is conducted in accordance with the detected current and a current indication value.
FIG. 1 is a block diagram of one example of the prior art. A PWM driving device 1 comprises a processor 2, a driver IC 3, an actuator 4, a sense resistance 5, a current sense circuit 6, and a comparator circuit 7. The processor 2 sends a drive indication signal to the driver IC 3. The processor 2 includes a logic circuit 8 and a digital-analog converter (DAC) 9. The logic circuit 8 generates a first control signal *EN from a drive signal DRVON generated in the processor 2 and an output signal *DTCR of the comparator circuit 7. The DAC 9 converts a target current indication value calculated in the processor 2 into an analog target current indication signal, and sends the target current indication signal to the comparator circuit 7.
FIG. 2 is a block diagram of the logic circuit of the prior art. The logic circuit 8 comprises a NAND gate 8a, a timer 8b, and an OR gate 8c. The NAND gate 8a receives the drive signal DRVON generated inside and the output signal *DTCR of the comparator circuit 7. The NAND gate 8a then outputs a NAND logic of the drive signal DRVON and the output signal *DTCR of the comparator circuit 7. The timer 8b receives the output signal *DTCR of the comparator circuit 7. The timer 8b operates in accordance with the output signal *DTCR of the comparator circuit 7, and outputs a high level for a predetermined period of time. The OR gate 8c outputs an OR logic of the output of the NAND gate 8a and the output logic of the timer 8b. The output signal of the OR gate 8c serves as the first control signal *EN.
FIGS. 3A to 3E show the operation of the logic circuit of the example of the prior art. FIG. 3A shows the drive signal DRVON; FIG. 3B shows the output signal *DTCR of the comparator circuit 7; FIG. 3C shows the output signal of the NAND gate 8a; FIG. 3D shows the output signal of the timer 8b; and FIG. 3E shows the first control signal *En, i.e., the output signal of the OR gate 8c.
As shown in FIGS. 3A and 3C, when the drive signal DRVON reaches the high level at time t1, the output of the NAND gate 8a reaches a low level.
As shown in FIG. 3B, the output signal *DTCR of the comparator circuit 7 falls at times t2, t3, and t4. The timer 8b detects the falls, and the output signal of the timer 8b reaches the high level for a predetermined period of time T0, as shown in FIG. 3D. The first control signal *EN is the OR logic of the output signal of the NAND gate 8a and the output signal of the timer 8b shown in FIG. 3D. Accordingly, the first control signal *EN has a waveform as shown in FIG. 3E.
The first control signal *EN shown in FIG. 3E is sent to the driver IC 3 as an inversion enable signal. The driver IC 3 further receives a second control signal DIR from the processor 2, and the second control signal DIR indicates a driving direction. The driver IC 3 supplies both ends of the actuator 4 with a potential difference in accordance with the first and second control signals *EN and DIR transmitted from the processor 2, so that a current starts flowing in the actuator 4.
FIG. 4 is a block diagram of the driver IC 3 of the prior art. The driver IC 3 comprises control logic 3a and a drive circuit 3b. The control logic 3a generates first and second drive control signals P and N in accordance with the first and second control signals *EN and DIR supplied to terminals T1 and T2 from the driver IC 3. The first and second drive control signals P and N are sent to the drive circuit 3b. The drive circuit 3b comprises transistors Q1 to Q4 and diodes D1 to D4. A terminal T3 is connected to the high potential side (the power source side), a terminal T4 is connected to a low potential side (the ground side), and terminals 5 and 6 are connected to the actuator 4.
FIG. 5 shows the operation of the control logic of the prior art.
When the first control signal *EN supplied from the processor 2 is at a low level while the second control signal DIR is at a high level, as shown in FIG. 4, the control logic 3a sets the first drive control signal P at the high level and the second drive control signal N at the low level. When the first drive control signal P is at the high level and the second drive control signal N is at the low level, the transistors Q1 and Q2 are turned on, and the transistors Q3 and Q4 are turned off. Here, the terminal T5 of the actuator 4 has a high potential, and the terminal T6 has a low potential. Accordingly, a current flows as indicated by a solid line in FIG. 4 (T3.fwdarw.Q1.fwdarw.T5.fwdarw.M.fwdarw.T6.fwdarw.Q2.fwdarw.T4).
When the first control signal *EN supplied from the processor 2 is at the low level while the second control signal DIR is also at the low level and the second drive control signal N is at the high level, the control logic 3a sets the first drive control signal P at the low level and the second drive control signal N at the high level. When the first drive control signal P is at the low level, the transistors Q3 and A4 are turned on, and the transistors Q1 and Q2 are turned off. Here, the terminal T6 of the actuator 4 has a high potential, and the terminal T5 has a low potential. Accordingly, a current flows as indicated by a broken line in FIG. 4 (T3.fwdarw.Q3.fwdarw.T6.fwdarw.M.fwdarw.T5.fwdarw.Q4.fwdarw.T4).
When the first control signal *EN supplied from the processor 2 is at the high level, the control logic 3a sets the first and second drive control signals P and N both at the low level. By doing so, the transistors Q1 to Q4 are all turned off, and both ends of the actuator 4 are put in a high-impedance state to block a voltage.
The control logic 3a is compensated so that the first and second drive control signals P and N do not reach the high level at the same time, preventing a case that the transistors Q1 to Q4 are all turned on.
As described above, the driver IC 3 can perform the PWM drive by supplying a voltage to both ends of the actuator 4 in accordance with the first control signal *EN from the processor 2.
The sense resistance 5 is connected to the ground terminal T4 in the driver IC 3. The current sense circuit 6 is connected to both ends of the sense resistance 5.
The current sense circuit 6 comprises resistances R1 to R4 and an operational amplifier OP1, which constitute a non-inverting amplifier circuit. The current sense circuit 6 outputs a voltage Vref1 and a level-shifted current sense signal in accordance with the voltages at both ends of the sense resistance 5. The output of the current sense circuit 6 is sent to the comparator circuit 7. The comparator circuit 7 receives the current sense signal from the current sense circuit 6, and the target current indication signal from the processor 2.
The current sense signal supplied from the current sense circuit 6 is sent to an inverting input terminal in the comparator circuit 7. On the other hand, the target current indication signal is sent to a non-inverting input terminal in the comparator circuit 7.
The comparator circuit 7 compares the target current indication signal supplied from the processor 2 with the current sense signal detected in the current sense circuit 6, and outputs a 2-digit signal at a high or low level. If the output from the current sense circuit 6 is larger than the target current indication signal supplied from the processor 2, the comparator circuit 7 outputs a low-level signal. If the output from the current sense circuit 6 is smaller than the target current indication signal supplied from the processor 2, the comparator circuit 7 outputs a high-level signal.
The comparison result of the comparator circuit 7 is sent to the processor 2. In accordance with an external control signal and the comparison result of the comparator circuit 7, the processor 2 outputs the first control signal *EN and the second control signal DIR to the driver IC 3.
FIGS. 6A to 6C show the operation in the prior art. FIG. 6A shows the target current indication signal and the current sense signal; FIG. 6B shows the output signal *DTCR from the comparator circuit 7; and FIG. 6C shows the waveform of the first control signal *EN.
If the current sense signal from the current sense circuit 6 becomes larger than the target current indication signal supplied from the processor 2 as shown in FIG. 6A, the output signal *DTCR of the comparator circuit 7 becomes a low-level signal as shown in FIG. 6B. When the output signal *DTCR is at the low level, the first control signal *EN supplied from the processor 2 to the driver IC 3 becomes a high-level signal at least for the predetermined period of time T0, as shown in FIG. 6C.
When the first control signal *EN is at the high level, the voltage supply to the actuator 4 is stopped. If a current has been flowing from the terminal T5 to the terminal T6 in the actuator 4, it flows into the power source through the route (T4.fwdarw.D4.fwdarw.T5.fwdarw.M.fwdarw.T6.fwdarw.D3.fwdarw.T3) shown in FIG. 4. If a current has been flowing from the terminal T6 to the terminal T5 in the actuator 4, it flows into the power source through the route (T4.fwdarw.D2.fwdarw.T6.fwdarw.M.fwdarw.T5.fwdarw.D1.fwdarw.T3) shown in FIG. 4.
When the first control signal *EN becomes a low-level signal, the voltage supply is resumed, and a current increases in accordance with the transient characteristics of the coils. In this manner, the voltage supply to the actuator 4 is started and stopped depending on the first control signal *EN. Here, the target current indication signal supplied from the processor 2 to the comparator circuit 7 is made large, so that the mean value of the current flowing in the actuator 4 becomes large. Thus, the torque in the actuator 4 becomes high accordingly.
FIG. 7 shows the characteristics of the mean current with respect to the target current indication value. As the target current indication signal rises, the driving period is prolonged, and the mean drive current is increased. Accordingly, the mean drive current has characteristics of changing linearly with respect to the target current indication signal, as indicated by a solid line in FIG. 7.
Since the comparator circuit 7 compares the output of the current sense circuit 6 with the target current indication signal, the characteristics of the mean drive current with respect to the target current indication signal are influenced by the characteristics of the current sense circuit 6.
Due to variations in the current sense circuit 6 and the DAC 9, crossover distortion (the non-linearity around the zero point of current) is caused as indicated by a broken line a and a dot-and-dash line b in FIG. 7. If the dead zone is too wide as indicated by the broken line a in FIG. 7, oscillation is caused in the servo control, even with an increased target current indication signal. In a case where zero-setting cannot be carried out for the current as indicated by the dot-and-dash line b in FIG. 7, a seek error might be caused.
To avoid the above problem, the resistances R3 and R4 of the current sense circuit 6 are used as variable resistances to adjust the linearity around the current zero point.
As described so far, the conventional motor driving circuit has problems that there are great variations in the components of the current sense circuit 6, and that crossover distortion is often caused due to the dead zone indicated by the broken line in FIG. 7.
Even when a discrete system is employed to reduce the variations in the components, there are problems that adjustment procedures are complicated, and that accurate adjustment cannot be carried out.